1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device for storing and holding information utilizing a polarization state of a ferroelectric film sandwiched between electrodes of a capacitor.
2. Description of the Related Art
A semiconductor memory device using a ferroelectric (hereinafter, referred to as a ferroelectric memory device) is a nonvolatile memory which stores data utilizing the polarization direction of the ferroelectric. FIG. 6 shows an exemplary conventional nonvolatile semiconductor memory device using this type of ferroelectric. See, for example, T. Sumi et al., 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 268-269.
The ferroelectric memory device shown in FIG. 6 includes a plurality of memory cells MC each including a capacitor Cs and a MOS transistor Qc. The capacitor Cs has two opposing electrodes and a ferroelectric film sandwiched by the electrodes. One of the electrodes of the capacitor Cs is connected to one of a source electrode and a drain electrode of the MOS transistor Qc. The plurality of memory cells MC are arranged in row and column directions.
A plurality of word lines WL.sub.0 to WL.sub.2m+1 are arranged to correspond to rows of the plurality of memory cells MC, so that each word line is connected to gate electrodes of the transistors Qc of the corresponding row of the memory cells MC. When any of the plurality of word lines WL.sub.0 to WL.sub.2m+1 is selected, the memory cells MC connected to the selected word line are put in a selected state.
A plurality of bit lines BL.sub.0 to BL.sub.n and a plurality of bit bar lines /BL.sub.0 to /BL.sub.n are arranged to correspond to columns of the plurality of memory cells MC, so that each of the bit lines and bit bar lines is connected to the other of the source electrode and the drain electrode of each MOS transistor Qc of the corresponding column of the memory cells MC.
A plurality of plate lines PL.sub.0 to PL.sub.m extending in the row direction are arranged every other row of the plurality of memory cells MC, so that each plate line is connected to the other electrode of each of the capacitors Cs of the corresponding two rows of the memory cells MC which is not connected to the corresponding transistor Qc (hereinafter, such an electrode of the capacitor Cs is referred to as a plate electrode).
A plurality of MOS transistors T.sub.0 to T.sub.2m+1 are arranged to correspond to the plurality of word lines WL.sub.0 to WL.sub.2m+1 so that gate electrodes of the plurality of MOS transistors T.sub.0 to T.sub.2m+1 are connected to the corresponding word lines WL.sub.0 to WL.sub.2m+1, source electrodes thereof are connected to the corresponding plate lines PL.sub.0 to PL.sub.m, and drain electrodes thereof are connected to a drive line DL.
A plate driving signal generation circuit 1 supplies a plate driving signal to the drive line DL.
The operation of the conventional ferroelectric memory device having the above configuration shown in FIG. 6 will be described with reference to FIG. 7.
FIG. 7 is a timing chart of the ferroelectric memory device shown in FIG. 6. In a standby state before a word line (e.g., the word line WL.sub.0) rises to a selected level (high level), the bit lines BL.sub.0 to BL.sub.n, the bit bar lines /BL.sub.0 to /BL.sub.n, and the drive line DL are in a grounding potential level. When the word line WL.sub.0 rises to a high level, the memory cells MC connected to the word line WL.sub.0 turn to a selected state, and the transistor T.sub.0 is turned on, to allow the plate line PL.sub.0 to be connected with the drive line DL.
The plate driving signal then becomes a high level to provide a plate driving voltage Vp1, which is applied to the plate line PL.sub.0. As a result, information stored in the memory cells MC connected to this plate line is read to the bit lines BL.sub.0 to BL.sub.n. The bit bar lines /BL.sub.0 to /BL.sub.n, which are paired with the bit lines BL.sub.0 to BL.sub.n, respectively, are selectively connected to reference cells (not shown) to generate a reference voltage level. The reference voltage is set at a potential just in the middle of potentials at the bit line generated when the information read from the memory cell MC is "1" and when it is "0". This setting is achieved by adjusting the size of a capacitor of each reference cell.
A voltage difference between the paired ones of the bit lines BL.sub.0 to BL.sub.n, and the bit bar lines /BL.sub.0 to /BL.sub.n is sense-amplified, to read outside the information stored in the memory cells in the selected state. Thereafter, the plate driving signal becomes a low level to provide a grounding potential, which is applied to the plate line PL.sub.0. This allows information to be written again in the memory cells in the selected state.
In such a ferroelectric memory device, the ferroelectric film of the capacitor Cs of each memory cell MC is provided with positive and negative induced polarization, to store information in the memory cell MC. The stored information is read by detecting the state of the induced polarization. For this detection, it is required to supply a predetermined potential, such as the potential Vp1, to the corresponding plate line as described above. Since the capacitor Cs is made of a ferroelectric, the capacitance value thereof tends to be greater than that of a conventional DRAM. Moreover, the plate lines are generally made of precious metal, such as Au, Pt, and Ru, for the conformity with the dielectric of the capacitors. It is difficult to thicken Such precious metal since the processability thereof is a problem. An attempt to increase the width of the interconnects (to compensate the poor thickness) will be disadvantageous for realizing miniaturization and thereby high-density construction. For these reasons, it is difficult to reduce the resistance of the interconnects. This increases the time constant of the plate lines, and thus increases the time required for driving the plate lines. As a result, high-speed operation of the conventional ferroelectric memory device is difficult.
Moreover, in the conventional ferroelectric memory device, since the plate lines are charged and discharged, power consumption increases.
Thus, as described above, the conventional ferroelectric memory device has a construction in which the plate lines are driven at a predetermined voltage for each access. This requires a long time for driving the plate lines, making it difficult to realize high-speed operation. Moreover, power consumption increases for charging and discharging of the plate lines.